Join Apple's Silicon Engineering Group (SEG) and be at the forefront of crafting the next generation of Apple's systems-on-chip (SOCs).
Our SOCs, featuring multi-billion transistors, are the heart of iconic devices like i Phones, i Pads, and Macs.
We're seeking highly skilled Senior Analog Layout Leads to contribute to the evolution of Analog/Mixed-Signal (AMS) circuits, covering Ser Des, PLLs, and sensors.
As a Senior Layout Lead, you'll play a crucial role in translating design concepts into silicon, collaborating closely with circuit designers, and leveraging sophisticated tools.
Your work will involve crafting custom analog designs to optimize the performance of Apple's extraordinary products.
In this dynamic and innovative environment, you'll have endless learning opportunities while collaborating across talented multidisciplinary teams.
This job is right for you if you are a self-motivated engineer passionate about working with cutting-edge technology.
You want to accelerate career growth, thrive in a results-oriented environment, and contribute to the development of revolutionary Apple products.
Description Senior Layout Engineers/Leads are pivotal in delivering Analog Mixed-Signal IP in a SOC flow.
You will collaborate with teams of highly skilled individuals to develop the next generation of world-leading SOCs.
Your responsibilities include crafting sophisticated layouts for mixed-signal and analog circuits, reviewing floorplans, and analyzing intricate circuits with circuit designers.
You'll run complete sets of design verification tools, plan/schedule work, and coordinate vital layout tradeoffs.
Interpretation of LVS, DRC, and ERC reports is key to finding the fastest way to complete the layout, exceeding engineering specifications and expectations.
Key Qualifications 10+ years of experience in analog/mixed-signal layout design, with a focus on deep submicron CMOS circuits and at least 3+ years in Fin FET technologies.
Programming/scripting knowledge in SKILL, Perl, TCL, Shell, and/or Python.
Familiar with Machine Learning and AI concepts.
Proven expertise in implementing analog layout designs, achieving tight matching, low noise, and low power consumption.
Must recognize failure-prone circuit and layout structures, have experience with analog and DFM best practices, and be able to identify the best approach to solving problems.
High proficiency in custom and standard cell-based floor-planning and hierarchical layout assembly.
Technical understanding of IR drop, RC delay, electromigration, self-heating, and coupling capacitance.
High proficiency in interpreting physical verification reports (DRC, ERC, LVS, etc.).
Experience using Cadence Virtuoso's advanced features (XL, EAD, APR, and Constraint Manager).
Excellent communication skills and ability to work with cross-functional teams.
Additional skill (plus): Cadence Innovus.
PCell creation experience.
Education & Experience BSEE, MSEE, CS or equivalent with 10+ years of relevant experience.
Concentration in Mixed-Signal and RF Integrated Circuits is helpful.
Apple is an Equal Opportunity Employer that is committed to inclusion and diversity.
We also take affirmative action to offer employment and advancement opportunities to all applicants, including minorities, women, protected veterans, and individuals with disabilities.
Apple will not discriminate or retaliate against applicants who inquire about, disclose, or discuss their compensation or that of other applicants.
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